Abstract

The recent emergence of multicore architectures and chip multiprocessors (CMPs) has accelerated the bandwidth requirements in high-performance processors for both on-chip and off-chip interconnects. For next generation computing clusters, the delivery of scalable power efficient off-chip communications to each compute node has emerged as a key bottleneck to realizing the full computational performance of these systems. The power dissipation is dominated by the off-chip interface and the necessity to drive high-speed signals over long distances. We present a scalable photonic network interface approach that fully exploits the bandwidth capacity offered by optical interconnects while offering significant power savings over traditional E/O and O/E approaches. The power-efficient interface optically aggregates electronic serial data streams into a multiple WDM channel packet structure at time-of-flight latencies. We demonstrate a scalable optical network interface with 70% improvement in power efficiency for a complete end-to-end PCI Express data transfer.

Highlights

  • Parallel computing environments require scalable interconnect solutions that provide the necessary bandwidth and latency to meet the computational needs of the system while maintaining manageable power dissipation figures

  • We propose a scalable and transparent network interface designed to address the issue of power dissipation by uniquely exploiting the parallelism and capacity of wavelength-division multiplexing (WDM) [9,10]

  • We experimentally demonstrate the end-to-end generation of a PCI Express (PCIe) link originating from a remote endpoint across the photonic network interface to a host computer in a transparent manner

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Summary

Introduction

Parallel computing environments require scalable interconnect solutions that provide the necessary bandwidth and latency to meet the computational needs of the system while maintaining manageable power dissipation figures. The recent emergence of multi-core architectures and chip multiprocessors (CMPs) for driving performance via increases in the number of parallel computational cores has accelerated the need for high bandwidth interconnect solutions in high-performance processors [1,2,3]. As off-chip bandwidth demands of CMPs continue to accelerate (a current generation IBM Cell processor can require up to 50.6 GB/s of throughput [3]), the power dissipation associated with multiple parallel electro/optical signal conversions grows rapidly. The proposed photonic network interface extends the capabilities of serial electronic protocols in high-performance computing systems by offering full bandwidth deployment in intra- and inter-chip optical interconnects by directly mapping serial streams onto multiple WDM channels in a highly power efficient manner. We experimentally demonstrate the end-to-end generation of a PCIe link originating from a remote endpoint across the photonic network interface to a host computer in a transparent manner.

Background
PCI Express link
Low-power photonic interface implementation
Complete PCI Express data transfer
Timing jitter
Photonic integrated interface for CMPs
Findings
Interface bandwidth scalability
Conclusion
Full Text
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