Low-power three-stage amplifier using active-feedback Miller capacitor and serial RC frequency compensation

Abstract

A low-power three-stage amplifier for driving large capacitive load is proposed. The feedback path formed by the active-feedback Miller capacitor leads to a high frequency complex-pole but a high Q-value, which significantly deteriorates the stability of the amplifier. The serial RC stage introduced as the second stage output load can optimize the resistor Rz and the capacitor Cz under fixed power and small compensation capacitor Ca, which brings about a suitable Q-value of the complex-pole and the gain-bandwidth product extension of the amplifier. The amplifiers were designed and implemented in a standard 65 nm CMOS process with capacitive loads of 500 pF and 2 nF, respectively. The post-layout simulation results show that the amplifier driving the 500 pF capacitive load can achieve a gain of 113 dB, a phase margin of 50.6° and a gain-bandwidth product of 5.22 MHz while consuming 24 μW from a 1.2 V supply. For the 2 nF capacitive load, the amplifier has a gain of 102 dB, a phase margin of 52.8°, a gain-bandwidth product of 4.41 MHz and a power of 43 μW. The total compensation capacitors are equal to 1.13 pF and 1.03 pF. The better figures-of-merits are 108 750 and 205 113(MHz×pF/mW). The layout areas are 0.064 mm×0.026 mm and 0.063 mm×0.027 mm. Compared with the CFCC scheme, the gainbandwidth product is extended by 1.6 times at CL=500 pF and Ca=1.1 pF.