Low Power Single-Bit Cache Memory Architecture

Abstract

A quantitative and yield analysis of single bit cache memory architecture has been analyzed. A single bit cache memory architecture is made up of a write driver circuit, SRAM cell, and sense amplifier. Apart from it, the power reduction technique has been applied over different blocks of single bit cache memory architecture such as sense amplifier and SRAM cell, to optimize the power consumption of the circuit. To check the robustness of the circuit monte Carlo simulation and process corner simulation also have been done. The conclusion arises that Single bit cache memory architecture having VMSA with forced stack technique over SRAM in an architecture consumes the lowest power (9.18 μW).