Low Power QC-LDPC Decoder Based on Token Ring Architecture

Mateusz Kuc,Wojciech Sułek,Dariusz Kania

doi:10.3390/en13236310

Mateusz Kuc, Wojciech Sułek + Show 1 more

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https://doi.org/10.3390/en13236310

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Journal: Energies	Publication Date: Nov 30, 2020
Citations: 1	License type: CC BY 4.0

Affiliation: Silesian University of Technology

Abstract

The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption. The key research concepts present an effective technology mapping of a QC-LDPC decoder to an LUT-based FPGA with many limitations. The proposed decoder architecture uses a distributed control system and a Token Ring processing scheme. This idea helps limit the clock skew problem and is oriented to clock gating, a well-established concept for power optimization. Then the clock gating of the decoder building blocks allows for a significant reduction in energy consumption without deterioration in other parameters of the decoder, particularly its error correction performance. We also provide experimental results for decoder implementations with different QC-LDPC codes, indicating important characteristics of the code parity check matrix, for which an energy-saving QC-LDPC decoder with the proposed architecture can be designed. The experiments are based on implementations in the Intel Cyclone V FPGA device. Finally, the presented architecture is compared with the other solutions from the literature.

Highlights

With the advancements in information technology, there is a constantly growing volume of data processing, for example, for medical, financial, social communication, and entertainment purposes.The increasing quality of multimedia content, like photos, videos and audio recordings has led to the need to process and transmit digital information in a faster and more efficient way
The proposed architecture of the Quasi-Cyclic Low-Density Parity-Check (QC-Low-Density Parity-Check (LDPC)) decoder based on Token Ring with a distributed control system and clock gating has been implemented in the Altera (Intel) Cyclone V Field Programmable Gate Array (FPGA) devices, for a number of different parity check matrices H of QC-LDPC codes
It is worth noting a significant reduction of the Pd for the architecture based on a Token Ring, with a simultaneous slight increase in the demand for Adaptive Logic Module (ALM) units

Summary

Introduction

With the advancements in information technology, there is a constantly growing volume of data processing, for example, for medical, financial, social communication, and entertainment purposes. The increasing quality of multimedia content, like photos, videos and audio recordings has led to the need to process and transmit digital information in a faster and more efficient way. In order to make, for example, a radio communication system errorless, special mechanisms called channel coding or Error Correction Coding (ECC) are needed. ECC makes it possible to correct a certain portion of transmission errors without the need for data retransmission. Such mechanisms are based on algorithms with relatively high computational complexity, and the elements responsible for data correction in high-speed communication technology are usually complex and energy-consuming

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