Low-Power Process and Temperature-Invariant Constant Slope-and-Swing Ramp-Based Phase Interpolator

Abstract

This article presents a process-and temperature-invariant high-resolution and highly linear low-power phase interpolator (PI) as an enabler for discrete-time spatial signal processors (SSPs) and for various mixed-mode RF transceiver architectures. Using current integration techniques, the proposed PI generates an adaptable constant slope-and-swing ramp signal to achieve significantly lower power suited for multiple antenna elements. Switched-capacitor-based bias generation enables tracking the ramp generator over process, voltage, and temperature enhancing the PI linearity. The 7-bit PI realized in the 65-nm CMOS technology can generate full delay range with a resolution of 4.88 ps at 1.6-GHz input frequency. The PI consumes a power of 503 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> W and occupies an active area of 0.021 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> with a jitter of 0.410 ps for a 1.6-GHz operation and measured DNL and INL of 0.52 and 0.52 LSB, respectively.