Low power pipelined 8-bit RISC processor design and implementation on FPGA

Abstract

RISC is a design technique used to reduce the amount of area required, complexity of instruction set, instruction cycle and cost during the implementation of the design. This article presents a simple 8-bit RISC processor design and implementation on Spartan-6 SP605 Evaluation Platform FPGA using Verilog Hardware Description Language (HDL). The processor is designed using Harvard architecture, having separate instruction and data memory. Its most important feature is that its instruction set is very simple, contains only 29 instructions, which is easy to learn. Another important feature is pipelining, used for improving performance, such that on every clock cycle one instruction will be executed. In RTL coding one can reduce the dynamic power by using clock gating technique, is used for specific modules which be clocked only when it is required. The proposed processor has 8-bit ALU, Two 8-bit I/O ports and Eight 8-bit general purpose registers and 4-bit flag register having zero flag, carry flag, borrow flag and parity flag and will work on 2.5 voltage supply. The interrupt module contains two interrupts, which are priority based and one of the interrupt is mask able. Another advantage of the proposed processor is that it executes programs with up to 262,144 instructions, such that any practical programs can be fitted into it. The proposed processor is physically verified on Xilinx Spartan-6 SP605 Evaluation Platform with 0.0564µs instruction cycle.