Low Power Parylene‐Based Memristors with a Graphene Barrier Layer for Flexible Electronics Applications

Abstract

AbstractLowering the programing power consumption is of importance to capacitate high‐efficiency flexible neuromorphic electronics. However, this remains particularly challenging for organic flexible memristor due to its high reset current. Here a robust route is reported to capitalize on graphene with native nanopores as a barrier layer for the parylene‐based flexible memristors, eventually conferring the devices to be operated with ultralow reset current (<50 µA) and programming power consumption (<150 µW). The graphene‐integrated memristor device in the architecture of Al/graphene/parylene/W (G‐memristor) lowers the reset current by ≈47 times and the programming power consumption by ≈14 times, respectively, as compared with those without the graphene barrier layer. Intriguingly, the conductive atomic force microscope characterizations reveal the metallic filamentary‐type switching mechanism of these G‐memristor devices, in which the intrinsic nanopores on graphene impart the formation of finer conductive filaments between Al electrode and parylene layer while suppressing the diffusion of mass metal atoms across the architecture. The integration of nanopores graphene as the barrier layer of organic memristors offers a promising route to low‐power flexible neuromorphic computing electronics.