Low-Power Non-Binary LDPC Decoder Design via Adaptive Message Length Control Exploiting Domain-Specific Information

Abstract

With the enhanced performance and convergence speed than their binary counterparts, NB-LDPC codes have been considered for emerging wireless communication and storage applications. However, one challenging issue to apply NB-LDPC codes in low-power embedded applications is the high decoding complexities. In this paper, we propose a comprehensive message length control technique that adaptively truncates decoding messages according to the domain-specific information. The number of arithmetic operations and memory accesses can be greatly reduced with shorter decoding messages. To implement the proposed technique, we propose a sequential decoder architecture which controls the decoding message length. Evaluation results show that the proposed technique can achieve significant power reduction than the conventional techniques while maintaining the same decoding performance.