Low Power Noise Multilayer PCB with Discrete Decoupling Capacitors Inside

Abstract

In this paper, we describe the design and implementation of the low noise interconnection (low power plane impedance) in multilayer boards using embedded discrete capacitor technology. To obtain the low noise solutions over a wide range of operating frequency, the overshoot resonances excited at some frequencies should be firstly analyzed. Some resonances make the signal and power integrity problems in the high speed digital boards. To solve these issues related with overshoot resonances, the equivalent circuit model for a PDN should be developed. It is well known that the transmission line matrix (TLM) model serves a proper design method for power delivery network (PDN) including the power/ground plane, via, capacitors, and so on. As using this TLM method, the power impedance and overshoot resonance for the designed PDN can be estimated. Therefore, the power impedance and some resonances on PDN can be easily approached and optimized for low noise interconnection design. The discrete capacitors are conventionally used to minimize the power impedance at any frequency band where the impedance of the decoupling capacitor is lower than that of the power/ground planes pair. However, the increase of equivalent series inductance (ESL) in the discrete capacitor degrades the low noise frequency bandwidth under the multilayer board environments. It is noted that the embedded discrete capacitor structure presented in this paper can be used to maintain the parasitic inductance of the decoupling capacitor as low as possible to decrease the overshoot of the resonance frequency. According to our experimental results, the resonance magnitude and power noise characteristic are from 15 ¿ to 1 ¿ and from -53 dBm to -64 dBm, respectively.