Low power & mobile hardware accelerators for deep convolutional neural networks

Abstract

This article provides a comprehensive review of recent developments in the field of computational hardware for mobile low power machine learning hardware accelerators. The article provides an introduction to neural networks, convolutional neural networks and details recent developments in state of the art deep convolutional neural networks. The key considerations in the design of low power hardware accelerators are discussed with reference to a conceptual system. Strategies for reducing the energy cost of memory access and computation in state of the art hardware accelerators are detailed. This includes techniques such as dataflow, reduced precision, model compression and sparsity. Recent reported digital mobile accelerators for deep convolutional neural networks with power consumptions of less than 3.3 W are observed to have 4x-20x better efficiency than the reference GPU accelerator at 16-bit precision, and can achieve 20x-1171x better efficiency at less than 4-bit precision. Efficiency improvements of 20x-1171x over a GPU is observed for reported mobile accelerators with reduced precision.