Low-Power Low-Area architecture of Probability Density Function Estimation for Histogram Equalization

Abstract

Estimation of Probability Density Functions (PDFs) in view of accessible information is critical issue emerging in various fields, for example, broadcast communications, machine learning, information mining, design pattern recognition and Personal Computer (PC) vision. In this paper, the Look-Up Table–Carry Select Adder-PDF (LUT-CSLA-PDF) mehod is implemented to increase system performance. The LUT is one of the fast way to recognize a complex function in the digital logic circuit. In this work, The FPGA (field programmable gate array) analysis, LUT, slices, flip flops, frequency are improved as well as ASIC (application specified integrated chip) implementation analysis an area, power, delay, Area Power Product (APP), Area Delay Product (ADP) are enhanced in LUT-CSLA-PDF technique compared to conventional methods.