Low power in-memory computing platform with four Terminal magnetic Domain Wall Motion devices

Abstract

The separation of memory and computing units in current Von-Neumann computer architecture leads to unwanted energy hungry data movement and insufficient memory bandwidth. Developing an energy efficient in-memory computing platform is promising to address such issues. Spintronic devices, utilizing electron spin as state variable for information processing and data storage, have demonstrated non-volatility, low power, zero leakage current and high area density advantages over conventional CMOS technology, which makes it an excellent candidate for future in-memory computing design. In this work, we propose a low power in-memory computing platform using a novel 4-terminal magnetic domain wall motion (4T-DWM) device, in which the proposed 4T-DWM device can be employed as both non-volatile memory cell and in-memory logic. The proposed design leads to the unity of memory and logic. Based on our device-circuit SPICE-level simulation, the proposed memory cell writing energy is one order lower than the standard one transistor one magnetic tunnel junction (MTJ) based memory design with writing speed of 1ns. Compared to state-of-the-art CMOS based full adder, the proposed 4T-DWM device based in-memory full adder consumes 3.2× lower power at 500MHz.