Low-Power Hyperspectral Anomaly Detector Implementation in Cost-Optimized FPGA Devices

Abstract

Onboard data processing for on-the-fly decision-making applications has recently gained momentum in the field of remote sensing. In this context, hyperspectral anomaly detection has received special attention since its main purpose lies in the identification of abnormal events in an unsupervised manner. Nevertheless, onboard real-time hyperspectral image processing still poses several challenges before becoming a reality. This is why there is an emerging trend toward the development of hardware-friendly algorithmic solutions embedded in reconfigurable devices. In this context, this work contributes to a hardware architecture that ensures a progressive line processing in time-sensitive applications limited by the scarcity of hardware resources. In this sense, we have implemented the state-of-the-art hardware-friendly line-by-line fast anomaly detector for hyperspectral imagery (HW-LbL-FAD) detector on a reconfigurable hardware for a real-time performance. Specifically, we have selected a cost-optimized field-programmable gate array (ZC7Z020-CLG484) to implement our solution whose results draw up a good tradeoff between the following three features: time performance, energy consumption, and cost. The experimental results indicate that our hardware component is able to process hyperspectral images of 825x1024 pixels and 160 bands in 0.51 s with a power budget of 1.3 W and costs around 150€.Regarding detection performance, the HW-LbL-FAD algorithm outperforms other state-of-the-art algorithms.