Low Power High-Speed Two-Stage Dynamic Comparator Circuit Design for Analog to Digital Converters

Abstract

When compared to typical two-stage dynamic latch comparators, this article describes a two-stage dynamic latch comparator that gives high speeds by consuming very little power. There are two stages in the proposed comparator: a dynamic latch and a pre-amplifier stage. In 32nm CMOS technology, the HSPICE tool is used to simulate the comparator circuit. Three distinct VDD supply input voltages i.e. 0.9 V, 1 V, and 1.1 V are used for the simulation and the performance parameters such as average power, propagation delay, power delay product, and power dissipation are investigated. Average power, propagation delay, power delay product, and power dissipation are found to be 7.37 µW, 0.148 µs, 38.1 fJ, and 0.257 µW, respectively, which are lower than conventional values.