Low power, high-performance reversible logic enabled CNTFET SRAM cell with improved stability

Abstract

Abstract With aggressive scaling of device feature size, performance of conventional MOS SRAM is affected and reliability, leakage power dissipation, and testing related issues arise due to short channel effects. So CNTFET device is promising and ideal candidate to replace existing MOS technology because of its excellent performance and high thermal stability. In this paper design and analysis of CNTFET SRAM cell, Reverse Logic enabled SRAM (RL-SRAM) and RL-SRAM with body bias is presented at 32 nm using Vdd 0.7 V. Adiabatic technique is incorporated in SRAM cell that uses reversible logic, plays an important role to reduce power consumption by recycling the energy stored at node capacitance instead of dissipating in form of heat. By incorporating of reversible logic with SRAM, 60.72% and 65.20% reduction in leakage power dissipation and improvement of 55.34% and 64.77% in delay is achieved for CNTFET RL-SRAM and RL-SRAM with body bias respectively in comparison of CNTFET SRAM cell. Results are also compared with previous work [1] , which shows significant improvement in average power consumption, delay, and leakage power dissipation is achieved using CNTFET SRAM cell design without affecting the system performance. Stability of the memory cell is also examined by using butterfly curve and N-curve analysis.