Low power, high speed and noise immune wide-OR footless domino circuit using keeper controlled method

Abstract

In this paper, a new circuit is proposed for enhancing the performance of the wide fan-in OR footless domino circuits in terms of noise immunity and speed. The proposed circuit is the modification of standard footless domino circuit by an adding keeper controlling network between the gate of the keeper transistor and the dynamic node. The keeper controlling network consists of a PMOS transistor, a diode and delay elements to control the keeper transistor. At the beginnings of evaluation phase for either low or high inputs, the keeper controlling network turns OFF the keeper transistor, which increases the circuit speed. In the same condition (when clock is high), if all the inputs of the pull down network are low then the noise immunity of the circuit gets increased. The proposed circuit and the other previously existing circuits are demonstrated through simulations using 90-nm CMOS technology for 4, 8, 16 and 32 inputs OR gate. The simulation results for 32 inputs OR gate show that the proposed circuit reduces the power consumption, delay, and power delay product by 31.42, 0.69, and 31.91%, and the noise immunity is increased by 0.23% as compared to the HS-domino circuit.