Low-Power Energy Harvesting Voltage Doubler Using CTLs Based on Inverse Class-F Configuration Compatible with Fifth Generation

Abstract

This paper introduces a highly efficient and low-power inverse class-F voltage doubler (VD) designed for radio frequency (RF) energy harvesting systems. Specifically tailored for mid-band 5G technology, the VD is designed for operation within the 1240–1300 MHz satellite band. The innovative design employs an inverse class-F architecture, incorporating a λ/8\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\lambda /8$$\\end{document} short-ended transmission line (TL) connected to the diode anode and a (λ/12\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$\\lambda /12$$\\end{document}) open-ended transmission line linked to the input of the voltage doubler. This configuration aims to reshape voltage and current waveforms, effectively reducing losses and series resistance in the diode. Dual-coupled transmission lines (CTLs) are utilized to provide passive voltage boosting at low-input power levels. The suggested voltage doubler is implemented using RO4003C substrate material with a dielectric relative permittivity (εr\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$${\\upvarepsilon }_{r}$$\\end{document}) of 3.38 and a thickness of 0.81 mm. Measured results demonstrate a minimum input return loss of − 29.3 dB at 1.25 GHz, operating seamlessly within a frequency band from 1.18 to 1.32 GHz. The measured conversion efficiency is 45.2% at an input power (Pin) of − 4dBm. Furthermore, the peak RF–DC efficiency reaches 50% at an input power of 0dBm. Simulated results predict a remarkable conversion efficiency of 60% and 68.7% at − 4dBm and 0 dBm, respectively. In addition to its exceptional performance, the suggested voltage doubler exhibits an experimental DC output voltage of 0.53 V at Pin=-10dBm\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$P_{{{\ ext{in}}}} = - 10{\ ext{dBm}}$$\\end{document} and a saturated DC voltage of 3.4 V at an input power of 10dBm under a load terminal resistance of 8 KΩ. Finally, the dimensions of the proposed voltage doubler are 25.3×10.5mm2\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$25.3 \ imes 10.5 {\ ext{mm}}^{{2}}$$\\end{document}.