Abstract
This paper enumerates new architecture of low power dual-edge triggered Flip-Flop (DETFF) designed at 180nm CMOS technology. In DETFF same data throughput can be achieved with half of the clock frequency as compared to single edge triggered Flip-Flop (SETFF). In this paper conventional and proposed DETFF are presented and compared at same simulation conditions. The post layout experimental results comparison shows that the average power dissipation is improved by 48.17%, 41.29% and 36.84% when compared with SCDFF, DEPFF and SEDNIFF respectively and improvement in PDP is 42.44%, 33.88% and 24.69% as compared to SCDFF, DEPFF and SEDNIFF respectively. Therefore the proposed DETFF design is suitable for low power and small area applications.
Highlights
The latest advancement in computing technology has set a goal of high performance with low power consumption for VLSI designer [1]
Post-layout simulation results show that the proposed DET flip-flop has 21.75μW average power dissipation that shows an improvement of 48.17%, 41.29% and 36.84% when compared with static output-controlled discharge Flip–Flop (SCDFF), DEPFF and SEDNIFF respectively
Proposed dual-edge triggered Flip-Flop (DETFF) has an improvement of 42.44%, 33.88% and 24.69% in terms of power delay product (PDP) as compared to SCDFF, DEPFF and SEDNIFF respectively
Summary
The latest advancement in computing technology has set a goal of high performance with low power consumption for VLSI designer [1]. An alternative clocking approach is based on the use of storage elements which are capable of capturing data on both rising and falling edges of the clock Such storage elements are termed as Dual-Edge Triggered Flip-Flops (DETFFs). In this scenario, same data throughput can be achieved at half of the clock frequency as compared to single edge triggered Flip-Flops [4]. Reducing the supply voltage is the most effective way to reduce power consumption of the design It decreases the speed of the designed circuit. These results are compared with conventional designs in terms of delay, power, PDP and area and Section 5 ends with conclusion
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