Low power design of FSMs by state assignment and disabling self-loops

Abstract

This paper deals with the low power design of synchronous finite state machines (FSM) with respect to a given sequence of primary input signals (pattern). We suggest a novel and practical synthesis approach to reduce switching activity by disabling particular self-loops combined with an appropriate state encoding. The required analysis of the FSM behaviour regarding to the pattern sequence is performed by an underlying profiling step. The experimental results show that the power can be considerably reduced but the obtained reduction depends decisively on both the FSM structure as well as the pattern sequence.