Low-Power Design of Double Edge-Triggered Static SOI D Flip-Flop

Abstract

In this paper, a double edge-triggered (DET), static SOI D flip-flop design suitable for low power and low area application is proposed. Silicon on insulator (SOI) is particularly good for low-power digital systems. Based on SOI technology instead of bulk silicon we realized a novel single edge-triggered (SET) static SOI D flip-flop using only ten transistors thus resulting in low-power consumption. Based on the SETDFF, a double edge-triggered D flip-flop is further constructed with an upper path and a lower path connected between the data input and an output node. Compared to single edge-triggered D flip-flop which processes data only at either the rising or falling transition of the clock, the DET D flip-flop doubles the rate of data thereby, increasing the data throughput. Simulation results indicated that the circuit is capable of significant power saving.