Low-power design and application based on CSD optimization for a fixed coefficient multiplier

Abstract

This paper presents a low-power design for a fixed coefficient multiplier, based on the canonic signed digit (CSD) method. The proposed technology overcomes the defects of the general CSD method by reducing system power and area substantially without additional logic. The theoretical basis and a design method are explained in detail in this paper. Our design technology was used to optimize a radio-frequency module. FPGA test results show that logic utilization is reduced by 25%, the total number of registers used is reduced by 23.02%, and the total block memory bits utilization is reduced by 20%. These results show that the proposed low-power design is an effective method.