Abstract

In this work, reconfigurable and reusable DTCWT OFDM modulator-demodulator based on Optimum Systolic Array (OSA) and Modified Distributive Arithmetic (MDA) algorithm is designed for low power underwater MODEM applications. The DTCWT-IDTCWT filters are designed considering integer 10-tap Q shift filter coefficients that are quantized and rounded off to achieve symmetry among filter coefficients. Multi stage DTCWT structure is used to perform 2560 subcarrier modulation and demodulation using MDA and OSA modules. The OSA structure is designed with optimum placement of Processing Elements (PE) and the MDA structure is designed to compute two filter outputs per module with Look up Table (LUT) of depth 8. The 2560 modulation is carried out using folded pipelined structure that comprises of two fold and four fold configurable modules. The reusable pipelined folded OFDM modulator-demodulator is implemented on Virtex-5 FPGA and operates at a maximum frequency of 248 MHz occupying less than 15% of LUT resources and consumes less than 1.33 W power.

Highlights

  • Inverse Dual-Tree Complex Wavelet Transform (DTCWT) performs Orthogonal Frequency Division Multiplexing (OFDM) modulation at the transmitter and DTCWT is used to retrieve symbols at the receiver

  • Architectures for DiscreteWavelet Transform (DWT) implementation on FPGA platform optimizing area, speed and power have been reported, that can be used for DTCWT implementation

  • Chao Cheng et al [8] have proposed a high-speed single stage architecture based on hardware efficient parallel finite impulse response (FIR) filter structures for the DWT calculation

Read more

Summary

Introduction

Inverse DTCWT performs OFDM modulation at the transmitter and DTCWT is used to retrieve symbols at the receiver. Chao Cheng et al [8] have proposed a high-speed single stage architecture based on hardware efficient parallel finite impulse response (FIR) filter structures for the DWT calculation. These structures differ in terms of size of arithmetic unit, on-chip memory, cycle period and average calculation time (ACT). Y = a3c0 + a1c1 + a1c2 + a1c3 + a0c4 y = a0c0 + a1c1 + a2c2 + a1c3 + a3c4 filter output y01 is generated by considering the filter coefficients ai1 = {a0, a3, a4, a2, a1} and input data bi is required. (5), with each of the expression are computed by PE that performs two operations, multiplication of terms ai & bi or ai & ci and accumulation of the multiplied outa ( x5 + x6 ) + a1 ( x7 + x8 ) 3 (a )

Optimum systolic array design
Modified distributive arithmetic
Comparison of resources
Folded Pipelined OFDM Modulator
Results and Discussion
Conclusion
Conflict of Interest
Full Text
Paper version not known

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.