Low power architecture for floating point MAC fusion

Abstract

With the proliferation of floating point computing applications, the demand for high performance, low power floating point hardware has increased. A new architecture for low power floating point multiply-accumulate fusion is presented. The proposed architecture minimises power consumption through transition activity scaling and data path simplifications. The switching activity function of the proposed MAF is represented as a four-state FSM. During any given operation cycle, only a limited set of functional subunits are active, during which time, the logic assertion status of the circuit nodes of the unused functional units are maintained at their previous states. Critical path delay and latency are reduced by incorporating data path simplifications and speculative rounding. The scheme offers a worst case power reduction of more than 49%.