Abstract
Flip-flops play an important role in building digital CMOS designs. Their design and optimization is critical for high-performance and low power systems. In this paper, we propose high-performance and low power flip-flops based on the explicit-pulsed flip-flop (EPFF). These new flip-flops eliminate the hazardous glitches associated with the original EPFF output. The Static-EPFF (SEPFF) is developed for low-power dissipation purposes; it reduces the power dissipation by 13.9%-15.7%, and it enhances the speed by 4.86%-7.87%. For high-speed objectives, the dual path single-transistor-clocked EPFF (STC-EPFF) achieves 21% enhancement in speed over EPFF at the expense of increased power dissipation (12%).
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