Low-power and high PPF feature synaptic transistors with 3D interface based on SnO2 nanofibers for neuromorphic application

Abstract

Featuring excellent computational rates and highly parallel computing, human brain-based neuromorphic devices have attracted the attention of more and more researchers. There have been numerous reports investigating the use of transistors to simulate synaptic functions; however, the majority of the dielectric and channel layers in these devices are layer-stacked structures, which are not conducive to the modulation of the active layers. Moreover, optimizing the paired pulse facilitation index is a critical factor in enhancing the short-term memory of synaptic devices and constructing high-precision synaptic systems, but it has received inadequate attention. In this study, we present a low-cost electrolyte-gated synaptic transistor with three-dimensional (3D) interfacial contacts, in which the channel layer is SnO2 nanofibers, and the 3D interface reduces the power consumption to 9.6 fJ. This study has simulated some important synaptic behaviors; importantly, the PPF value is as high as 223%, which is related to the slow kinetics of sodium ions. In addition, the Ebbinghaus forgetting curve and its application to image memory are also simulated. These findings provide valuable insight for the future development of complex neuromorphic systems.