Low Power and Area Efficient Phase Accumulator for DDFS Applications

Abstract

This paper presents a low power and area efficient ‘phase accumulator’ (PACC) with 32-bits frequency resolution and 10-bits phase resolution. The PACC is derived based on primitive phase accumulator architecture, using a novel carry propagate adder (HCPA). The HCPA consists 8 full adder (FA) cells in its carry propagate chain. Out of 8 FA cells, the most significant bit (MSB)-FA (MFA) cell uses 28-transistors and each of the remaining 7 least significant bit (LSB)-FA (LFA) cells uses 16-transistors. This hybrid combination of MFA with LFA cells provide both low as well as low power dissipation benefits. The proposed PACC has a maximum frequency of operation (f max ) =410 MHz, consumes an average power dissipation of 80.56 µWatts at supply (V dd ) =1.2 V and has a total transistor count (TC)=2096. All the circuit simulations are carried out using Cadence’s Spectre simulator based on 90 nm technology node.