Low Power Adder Based Digital Filter for QRS Detector

L Murali,T Manigandan,D Chitra

doi:10.1155/2014/405893

L Murali, T Manigandan + Show 1 more

Open Access

https://doi.org/10.1155/2014/405893

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Abstract

Most of the Biomedical applications use dedicated processors for the implementation of complex signal processing. Among them, sensor network is also a type, which has the constraint of low power consumption. Since the processing elements are the most copiously used operations in the signal processors, the power consumption of this has the major impact on the system level application. In this paper, we introduce low power concept of transistor stacking to reduce leakage power; and new architectures based on stacking to implement the full adder and its significance at the digital filter level for QRS detector are implemented. The proposed concept has lesser leakage power at the adder as well as filter level with trade-off in other quality metrics of the design. This enabled the design to be dealt with as the low-power corner and can be made adaptable to any level of hierarchical abstractions as per the requirement of the application. The proposed architectures are designed, modeled at RTL level using the Verilog-HDL, and synthesized in Synopsys Design Compiler by mapping the design to 65 nm technology library standard cells.

Highlights

Signals are natured through the analog and digital types
The results of the variable bit width adders are tabulated in Table 1 and their impact in the digital filter can be observed from Table 2
The importance of computational logic “adder” in the complex signal processing applications is proved in this paper, by incorporating the adder in the digital filter of the QRS detector

Summary

Introduction

During the last decade the technology has yielded the powerful, smaller, faster, and cheaper digital computers and special-purposed digital hardware are developed Such digital circuits are made possible to develop highly sophisticated systems capable of performing complex signal processing functions and tasks which are too expensive and difficult to be handled by the analog circuitry. As a result new sensing and monitoring devices for healthcare and the use of wearable/wireless devices for clinical applications have been witnessed during the last decade [3] Such devices are technically called or characterized as body sensor networks. We propose architectures of the processing element for digital filter, which is the extensively used component in complex signal processing applications. In this paper we are addressing the issue for the low power filter architecture of the processing block “QRS detector” used in biomedical sensor networks

BSN Low Power Requirement

Architecture

Results and Observations

Conclusion