Abstract
Background: An adder is the basic building block of any circuitry. Most ripple carry adders suffer from carry rippling which constrains its performance due to increased delay though they occupy less area. Objectives: To design and implement a high speed adder to overcome the carry rippling, which should consume less power and also operate at higher frequency. Method: Squareroot CSLA architecture is designed by replacing ripple carry adder with of Add- One Circuit (AOC) to minimize the area and carry rippling delay. Improved Pass-Gate Adiabatic Logic (IPGL) is incorporated in the proposed SCLSA to reduce power and to increase frequency of operation. Cadence Virtuoso and Spectre is used to design and simulate the adder circuits in CMOS 180nm technology. Findings: We proposed SCSLA adder, which consumed 89% lesser power compared to the reference architecture at 400 MHz operating frequency with a power saving factor of 7.3. Results were verified by simulating up to 1 GHz frequency. Novelty: Incorporation of AOC in the design of square-root CSLA with adiabatic logic (IPGL) incorporated results in lesser power consumption and also adder operates in the higher frequency (GHz). Keywords: AL; AOC; BEC; IPGL; low power
Highlights
The trend towards low-power IC design is driven by the increasing demand for long-life portable devices
High-speed and low power SCSLA with Binary to Excess1 Converter (BEC) and AddOne Circuit (AOC) is realized in Improved PassGate Adiabatic Logic (IPGL) and in static CMOS logic
SCSLA reduced the delay by 80% when compared to a ripple carry adder
Summary
The trend towards low-power IC design is driven by the increasing demand for long-life portable devices. A N+1-bit BEC is used instead of the N-bit RCA in the modified architecture to decrease area and power consumption. Objectives: To design and implement a high speed adder to overcome the carry rippling, which should consume less power and operate at higher frequency. Method: Squareroot CSLA architecture is designed by replacing ripple carry adder with of AddOne Circuit (AOC) to minimize the area and carry rippling delay. Improved PassGate Adiabatic Logic (IPGL) is incorporated in the proposed SCLSA to reduce power and to increase frequency of operation. Findings: We proposed SCSLA adder, which consumed 89% lesser power compared to the reference architecture at 400 MHz operating frequency with a power saving factor of 7.3. Novelty: Incorporation of AOC in the design of square-root CSLA with adiabatic logic (IPGL) incorporated results in lesser power consumption and adder operates in the higher frequency (GHz)
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