Abstract
Modern digital programmable modems require very stable clock generation at the transmit side to provide a clean spectrum and to guarantee bit count integrity in the presence of prolonged signal outages. On the other hand, such modems need also to carry various traffic rates which in turn require a programmable clock. This paper covers the design performance and analysis of a high frequency, DDS driven, third order DPLL. The paper identifies the noise sources in such a design which differ from the traditional VCO driven PLL noise sources. Furthermore the analysis and hardware implementation of a low cost, low phase noise, wide range, high frequency and programmable clock generator are presented in the paper.
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