Low noise figure CMOS 2-port active inductor using LC resonator

Abstract

One important issue related to the standard CMOS technology is a low-resistivity silicon substrate that results in low Q-factor for the passive spiral inductor. Therefore, active inductors have widely studied and applied to different range of RF circuit applications due to high-Q, low insertion loss, small size, and inductance tenability [1]. However, the conventional active inductors have also some drawbacks such as high noise figure, poor linearity, and high power consumption [2]. Moreover, most of the previously studied active inductors were basically grounded-type 1-port network. In this paper, a design of novel active 2-port inductor using LC parallel resonator is presented. The parasitic capacitances are decreased by adding parallel L f and C f to gates of M 1 and M 2 , as a result the Q-factor of overall circuit can be improved. The simulation was performed in Cadence Spectre by using SP simulation. The overall circuit size of the proposed active inductor is 0.45mm × 0.5mm including the pads, where the active area occupies only 0.2mm × 0.15 mm. The proposed circuit consumped 3.6mW DC power at 1.8V supply voltage. On wafer probing was used to characterize 2-port S-parameters of the proposed circuit and also a pad de-embedding method was used for accurate measurements. Figs. 1 and 2 show the simulated and measured inductances and Q-factors of the fabricated circuit. From an experiment, it is found that the inductance and Q-factor are higher than 2 nH and 50, respectively, in the frequency range of 1–6 GHz. The simulated and measured noise figure of the fabricated circuit is shown in Fig. 3. The measured noise figure is less then 12 dB in constant inductance range. The proposed circuit provides high inductance, Q-factor, low DC power consumption, and low noise figure over wide frequency range. The proposed 2-port active inductor is applicable in various RF circuits and systems such as coupler, RFIC filters, power dividers, and LC-VCO.