Low Noise and Fast Locking Phase Locked Loop Using a Variable Delay Element in the Phase Frequency Detector

Abstract

Low power consumption, low phase noise and dead zone free operation are the vital performance parameters in a high performance Phase Locked Loop (PLL). These parameters are tailored by using a variable controlled delay element in the reset path of the Phase Frequency Detector (PFD) of a Charge Pump PLL (CPLL). The overall PFD delay is maintained at a small positive value to avoid dead zone at lower phase noise by using feedback from one of the inputs of the charge pump. The performance analysis carried out in Cadence design environment is reported in this work.