Low memory usage architecture for 3D graphics based on scan-line rendering

Abstract

We propose a novel 3D graphics architecture based on scan-line rendering. Scan-line rendering does not require a frame buffer and depth buffer, therefore it can reduce memory usage as compared with the widely used frame buffer architecture. On the other hand, scan-line rendering requires a huge volume of memory access. Some algorithms to solve this problem were proposed in the field of 2D graphics, but more improvement to reduce memory usage is required for embedded devices of 3D graphics. To achieve low memory usage in 3D rendering, we developed an effective algorithm to restructure polygon data in the scan-line order. Furthermore we developed a novel vertex cache that utilizes the characteristics of scan-line rendering. As a result, we succeeded in reducing memory usage by about 80% in comparison with the frame buffer method while maintaining the volume of memory access at the same level.