Low-Leakage and Variable V HOLD Power Clamp for Wide Stress Time Range From ESD to Surge Test

Abstract

In recent years, on-chip clamp designs for enhancing destructive immunity of ICs mounted on systems against residual currents of system level immunity tests have been proposed. To cope with a long duration pulse (several tens μs) such as a surge immunity test is one of the issues of the system level on-chip clamp. A clamp combined RC-trigger and static trigger is one approach to achieve both a low voltage clamping against component level ESD events and system level surge protection. However, the combined clamp using the conventional static trigger is difficult to achieve both a high current capability against the long pulse event and a low standby leakage current. This work presents a combined clamp that overcome the trade-off between the long pulse current capability and the standby leakage current using a variable holding voltage technique. The proposed clamp achieves the higher current capability against the long pulse event without increasing the standby leakage by holding voltage lowering while keeping a higher trigger voltage. It can contribute to increase PCB design freedom and to protect ICs efficiently from wider time range immunity tests.