Low-leakage analog switches for low-speed sample-and-hold circuits

Abstract

In this paper, two leakage-combating analog switches for low-speed sample-and-hold (S/H) circuits are proposed. In conventional low-leakage switch, the potential drop along MOSFET is clamped to zero to suppress sub-threshold leakage. Based on this switch, the proposed leakage-combating analog switches can suppress p-n junction reverse-biased leakage by clamping the potential drop along parasitic p-n junction to zero. The proposed two switches are designed and fabricated with a 0.13 μm CMOS process in a prototype chip. The experiment results illustrate that the order of magnitude of the leakages from the proposed two switches only change from 10−15 A to 10−12 A in the temperature range from −20 °C to 120 °C, which is many times lower than that of the traditional switch. FFT simulations of the S/H circuits using the proposed switches are performed. On the condition of 0.01 kS/s and 100 °C, the THDs of the S/H circuits with these proposed switches are −53.98 dB, −61.09 dB respectively. The proposed switches are suitably applied in low-speed S/H circuits.