Low Latency Scheduling of Point Multiplication Featuring High Speed GF (2m) Multiplier Suitable for FPGA Implementation

Abstract

Point Multiplication (PM) is the most tedious and timeconsuming operation in Elliptic Curve Cryptography (ECC). Performing PM using a standalone hardware platform – the Field Programmable Gate Array (FPGA) is much necessary for high speed, secured communication. In this paper, we employ Lopez-Dahab (LD) Montgomery PM algorithm to perform PM faster, resisting the side channel attacks. We propose a careful scheduling of LD algorithm to reduce the number of clock cycles; thus reducing latency. Speed of PM fully depends on the speed of finite field multiplier. We implemented the finite field Montgomery modular multiplier in several FPGAs and found that Virtex6 FPGA achieves the highest speed (14.81 ns).