Low Latency Area-Efficient Distributed Arithmetic Based Multi-Rate Filter Architecture for SDR Receivers

Abstract

In software defined radio (SDR) receivers, sample rate conversion (SRC) and channelization are two computational intensive tasks. Coefficient-less cascaded-integrator-comb (CIC) filters achieve SRC with low computational complexity, but the design of its gain droop compensation filter involves coefficients. These coefficients vary with the change in radio standards. In this paper, an architecture for variable digital filter (VDF) for gain droop compensation employing a set of fixed coefficient sub-filters and multi-dimensional polynomials in terms of spectral parameters is realized based on distributed arithmetic (DA). As the coefficients in the sub-filters are fixed, the proposed method uses ROM-based LUTs giving rise to low computational complexity. The proposed DA–VDF filter is synthesized on an application specific integrated circuit (ASIC) employing CMOS 90[Formula: see text]nm technology using Synopsis Design Complier. The proposed architecture achieves low latency at a reduced area delay product (ADP) of 78% and an efficiency of 72% in energy per sample (EPS) when compared with the conventional MAC-based architecture.