Low Latency and Area Efficient Very Large Scale Integration Architecture of 2-Dimensional Bicubic Interpolation using Carry Save Adder Based Fast Multiplier

Abstract

Presently, real-time image processing is gaining increasing popularity, specifically in the field of satellite imaging and medical imaging. Naturally, researchers are increasingly being inclined to design dedicated hardware for imaging methods to aid real-time processing in a cost-effective way. Likewise, several VLSI architectures have already been designed for a variety of imaging methods. But, in spite of being a significant and popular imaging method, the image interpolation has no such notable dedicated VLSI architecture so far. Image interpolation has vast applicability ranging from image inpainting to image registration. In all such applications, the image interpolation part has been performed by software-based implementations. To alleviate the issue, a dedicated VLSI architecture 2D bicubic interpolation has been designed. The proposed bicubic architecture is based on state-of-the-art VLSI architectures for performing square and cube operations following vedic mathematics. Furthermore, all the adders used in the proposed design are judiciously developed to increase the speed retaining an acceptable area and power consumption. The proposed architecture is realized in the xilinx vivado 18.2 tool. The simulation results exhibit satisfactory performances. The quality of the proposed bicubic architecture has also been successfully tested by on board testing using the xilinx ZCU104 board to verify the viability of the design to be applied in real-time imaging applications.