Low-k Integration Using Metallic Hard Masks

Abstract

For the 45 nm interconnect technology node, porous dielectric materials (p-SiOCH) have been introduced, leading to complex integration issues due to their high sensitivity upon FC etching and ashing plasma exposure [1, 2]. Thanks to Metallic hard mask (MHM) integration high selectivities towards dielectric materials (>100:1) can be reached and minimizes exposure of p-SiOCH films to ashing plasmas. However MHM such as TiN generates other issues such as i) metal contamination in the patterned structures and ii) growth of metal based residues on the top of the hard mask [3, 4, 5]. The residues growth, which is air exposure time dependent, directly impacts the yield performance with the generation of via and line opens [.