Low-jitter PLL based on symmetric phase-frequency detector technique

Abstract

A low-jitter phase-locked loop (PLL) with a symmetric phase frequency detector has been proposed. The phase-frequency detector is composed of only two symmetric XOR gates. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45 degrees. The PLL was fabricated in a 0.18 μm CMOS technology. Measured phase noise of the PLL output at 500 kHz offset from the 5 GHz center frequency is ?102.6 dBc/Hz. The circuit exhibits a low rms jitter of 2.06 ps and a capture range of 280 MHz. The power dissipation excluding the output buffers is only 21.6 mW from a 1.8 V supply.