Low-Jitter Design for 25-Gb/s CMOS-Based Optical Interconnects

Abstract

Jitter of a 25-Gb/s optical link is numerically and experimentally analyzed. The numerical analysis shows that a 25-Gb/s optical transceiver needs retiming circuits in its transmitter and receiver in order to satisfy the targeted jitter budget of the optical link. Because the random jitter (RJ) largely contributes the total jitter of the 25-Gb/s optical link, an equation for calculating the RJ caused by relative intensity noise (RIN) was experimentally derived. According to the calculated RJ, the rise and fall times of an optical transmitter must be shortened to less than 19 ps to satisfy the targeted total jitter (less than 0.6 UI) at vertical-cavity surface-emitting laser (VCSEL) temperature of 80 °C. Moreover, a CMOS-based optical link, which consists of a VCSEL and a photodiode operating at 850-nm wavelength, a CMOS laser diode (LD) driver, and a CMOS transimpedance amplifier, was developed. The LD driver applies an asymmetric equalizer to shorten the fall time because nonlinear effects of a VCSEL generally make the fall time longer than the rise time. The experimental analysis of the developed optical link demonstrated total jitter of 0.58 UI (excluding deterministic jitter of an electrical interface) at data rate of 25 Gb/s.