Low Feedback Sampling Rate Digital Predistortion for Wideband Wireless Transmitters

Abstract

A novel digital predistortion (DPD) with an ultralow feedback sampling rate is proposed for wideband wireless communications. Analytical groundwork is carried out to support the rationale of the proposed method. Due to the power amplifier (PA) spectral expansion, the sampling rate of the feedback loop in the DPD architecture generally requires several times the input signal bandwidth, which presents challenges for the analog-to-digital converter, especially in broadband applications. In order to remove this bottleneck in real-world implementation, a forward behavioral modeling method with low-rate aliasing PA output signals is adopted to estimate the model coefficients. The obtained coefficients are then used to predict the high-rate PA output, using the input signal with an adequate sampling rate, and to further generate the predistorter for the nonlinear PA with the conventional indirect learning architecture. To validate the proposed method, different PAs driven with a 40-MHz two-carrier Long Term Evolution are used for linearization purposes. Experimental results based on the instrument platform show that the proposed algorithm achieves almost equivalent results with only a 2.5 Msamples/s feedback sampling rate. Further experimental verification is also demonstrated on an FPGA platform, which achieves an adjacent channel power ratio that is better than −47 dBc for 40-MHz signals with a feedback sampling rate of 20 Msamples/s.