Low delta-I noise CMOS circuits based on differential logic and current limiters

Abstract

Switching noise is becoming an important constraint in mixed signal design. In this paper we present an approach to implement combinational circuits that generate low levels of delta-I noise by obtaining a trapezoidal current waveform shape. We use a differential logic (ECDL) together with current limiters to implement a 4/spl times/4 multiplier. We present the results of the simulation of this multiplier and the comparison with the static complementary-metal-oxide semiconductor (CMOS) implementation.