Low crosstalk packaging design for Josephson logic circuits

Abstract

Theoretical and experimental studies are accomplished for inductive crosstalk noise reductions at Josephson chip-to-card connectors. This noise is induced by large AC power and high switching speed signal currents. The crosstalk mechanism was analyzed using a Partial Element Equivalent Circuits Model. Ground inductance causes not only crosstalk noise between connectors but also ground fluctuation noise inside the chip. This ground noise is large enough to cause false logic operations. Test chips and cards with improved connectors were produced for an experimental evaluation. Power crosstalk noise was measured using Josephson sampling circuits fabricated on the chip. The crosstalk noise - signal level ratio was less than 2.5%, when 250 MHz, 50 mA power currents were supplied. Crosstalk noise between neighboring signal connectors was also reduced to negligible level, including the worst case. These results favorably agree with calculations. This low crosstalk packaging design can be applied to high speed Josephson logic systems.