Low-Cost Strategy for Bus Propagation Delay Reduction

Abstract

We propose a strategy to reduce the propagation delay of microprocessors’ digital bus lines at very low costs in terms of area overhead, power consumption and power-delay product. Likewise some solutions adopted in industry nowadays, our strategy inserts in the bus lines repeaters implemented as a chain of inverters with increasing size. In this paper, we derive new expressions to determine the optimum number of inverters to be used within each repeater, and the optimum number of repeaters to insert in the bus lines. Our derived expressions yield to bus implementations with significant lower cost in terms of area overhead and power consumption than alternative solutions in literature. Considering a 32 nm technology as a significant example, we show that, compared to the traditional solution that inserts repeaters implemented as a single inverter, our strategy enables reductions up to 84% in terms of area overhead, up to 65% in power consumption, and up to 66% in power-delay product. Compared to three recent alternative solutions in the literature, our strategy enables reductions up to 88% in terms of area overhead, up to 48% in power consumption, and up to 43% in power-delay product. Therefore, our approach is particularly suitable to the growing market of mobile applications that require low cost in terms of power consumption and chip area.