Abstract
A low cost, high-speed architecture for the computation of the binary logarithm is proposed. It is based on the Mitchell approximation with two correction stages: a piecewise linear interpolation with power-of-two slopes and truncated mantissa, and a LUT-based correction stage that correct the piecewise interpolation error. The architecture has been implemented in an FPGA device and the results are compared with other low cost architectures requiring less area and achieving high-speed.
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