Low-Cost FPGA TDC With High Resolution and Density

Abstract

Time-to-digital converter (TDC) implemented in field programmable gate array (FPGA) has been developed for years and obtained superior performance. In an application with large amount of channels, tradeoff must be weighed between performance and cost if TDC is implemented in FPGA. Massive channels with high event rate also lead to big challenges for high data rate transmission in real time. Thus, it has great significance to develop time digitizers that accommodate high data rate with satisfying resolution and cost. In this paper, a TDC prototype with sandwich structure implemented in low-cost FPGA is presented. It contains 320 time measurement channels (ten TDC daughter cards) and can be used as digitizer for evaluating super module detectors in compressed baryonic matter time-of-fight experiment. Gigabit transceiver integrated in FPGA is utilized to support over 1-Gb/s data rate of a single TDC daughter. Preliminary tests show rms of leading edge measurement is better than 15 ps, and that of TOT measurement implemented by a single channel is better than 28 ps.