Low cost flip chip bumping technologies

Abstract

The 97Pb/3Sn solder bump flip chip metallurgy based on evaporative technology is one of the driving factors of miniaturization in portable electronic products, due to its size and its compatibility with surface mount technology. However, it is a relatively high cost IC packaging option due to the inherently expensive bumping cost, coupled with the high PCB cost which requires 63Sn/37Pb eutectic bumping. Various low cost bumping options have therefore been developed: printed solder bumping, electroplated eutectic solder bumping, gold stud bumping and electroless Ni/Au bumping. The bumping methods and assembly methods for these flip chips on to substrates are described and presented. The gold (Au) stud bump, which is based on wire bonding technology, offers a low cost flip chip solution for low I/O count ICs. The unconventional method of assembling this Au stud bump flip chip on a substrate based on direct thermocompression technology is presented in detail. Finally, the electroless Ni/Au bump, used in conjunction with anisotropic conductive paste or film, is also presented. This combination is expected to yield the lowest cost flip chip option.