Low‐cost and two‐cycle hardware structures of PRINCE lightweight block cipher

Abstract

SummaryIn this paper, low‐cost and two‐cycle hardware structures of the PRINCE lightweight block cipher are presented. In the first structure, we proposed an area‐constrained structure, and in the second structure, a high‐speed implementation of the PRINCE cipher is presented. The substitution box (S‐box) and the inverse of S‐box (S‐box−1) blocks are the most complex blocks in the PRINCE cipher. These blocks are designed by an efficient structure with low critical path delay. In the low‐cost structure, the S‐boxes and S‐boxes−1 are shared between the round computations and the intermediate step of PRINCE cipher. Therefore, the proposed architecture is implemented based on the lowest number of computation resources. The two‐cycle implementation of PRINCE cipher is designed by a processing element (PE), which is a general and reconfigurable element. This structure has a regular form with the minimum number of the control signal. Implementation results of the proposed structures in 180‐nm CMOS technology and Virtex‐4 and Virtex‐6 FPGA families are achieved. The proposed structures, based on the results, have better critical path delay and throughput compared with other's related works.