Low Complexity SST Viterbi Decoder

Abstract

Reducing the complexity and power consumption of the Viterbi decoder is one of the important design goals for high throughput wireless systems. Recently, a low complexity decoding algorithm was proposed to reduce the average number of ACS (Add Compare Select) operation of the Viterbi algorithm (VA) using the information of syndrome. Unfortunately, it has two limitations: the large computation overhead and the large memory requirement, which prevent it from the practical VLSI implementation. In this work, we propose an approach which facilitates the implementation of this reduced complexity algorithm by building it on the Scarce State Transition (SST) Viterbi decoding scheme. The proposed scheme achieves the similar complexity reduction while facilitates the low power implementation. Simulation results show that over 80% computation reduction can be achieved while the bit-error-rate (BER) performance of the VA is maintained.