Abstract

We propose and demonstrate a new low-complexity hardware architecture and digital signal processing (DSP) implementation for coherent reception of Nyquist frequency division multiplexed (Nyquist-FDM, digital subcarrier multiplexing) signals in real time. Key to achieve lowest complexity is the combination of an optimized frequency domain and time domain processing block. In the frequency domain processing, we combine subcarrier equalization and timing recovery with a noninteger oversampling ratio of 16/15. In the time domain, we take advantage of polar coordinate processing for the carrier recovery to avoid complex multiplications. The receiver is optimized for flexible operation and allows the adaption of filter coefficients and modulation format between 4QAM, hybrid 4/16QAM, and 16QAM within one clock cycle. The efficiency of the DSP is demonstrated by a real-time coherent receiver implementation on a single FPGA and is experimentally evaluated. Despite of the limited hardware resources, the receiver can detect a 30 GBd Nyquist-FDM signal with four subcarriers and a net data rate of 60 Gb/s (4QAM), 90 Gb/s (4/16QAM), or 120 Gb/s (16QAM) sampled with 32 GSa/s and demodulate one of the subcarriers at a time. Transmission of 300 km through standard single mode fiber is demonstrated with a BER below the soft-decision forward error correction limit.

Highlights

  • E FFICIENT real-time receivers and their low complexity implementation are key towards large-scale deployment of coherent technologies in generation compact optical networks

  • The multi gigabit transceivers (MGT) deserialize each lane by a factor of 32, which results in a total of 1536 parallel bits processed with a clock speed of 250 MHz

  • We proposed and demonstrated a new coherent hardware architecture. It combines frequency domain processing with noninteger oversampling for timing recovery and Nyquist-FDM subcarrier equalization with an efficient time domain processing in polar coordinates for carrier recovery

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Summary

INTRODUCTION

E FFICIENT real-time receivers and their low complexity implementation are key towards large-scale deployment of coherent technologies in generation compact optical networks. This increases the tolerance towards optical filtering in reconfigurable add-drop multiplexer systems [22] Another advantage is the simplification of the digital chromatic dispersion compensation filter since the filter length scales quadratic with the symbol duration [21]. BAEUERLE et al.: LOW-COMPLEXITY REAL-TIME RECEIVER FOR COHERENT NYQUIST-FDM SIGNALS. We propose and demonstrate a new efficient hardware architecture for coherent reception with 32 GSa/s and a non-integer oversampling of 16/15. It enables the implementation and real-time demonstration of a Nyquist-FDM receiver on a single FPGA. This work is in part based on earlier work related to the first FPGA-based coherent multi-format real-time NFDM receiver [30], [31] and supplies a detailed insight into our DSP architecture

Digital Signal Processing
ADC-FPGA Interface
Complexity and Hardware Utilization
Experimental Setup
Experimental Results
Findings
CONCLUSION
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